1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to an array substrate for an LCD device having a reduced leakage current and a method of fabricating the same.
2. Discussion of the Related Art
In general, a polycrystalline silicon thin film transistor (p-Si TFT) has higher field effect mobility and lower photocurrent than an amorphous silicon thin film transistor (a-Si TFT). Accordingly, a p-Si TFT is advantageous for use as a switching element in high resolution liquid crystal display (LCD) devices and projection systems. In addition, because the p-Si TFT has a self-aligning structure, the p-Si TFT has a lower level shift voltage than the a-Si TFT. Further, because the p-Si TFT may be a negative (N) type and a positive (P) type, a complementary metal-oxide-semiconductor (CMOS) circuit can be formed using the p-Si TFT.
Polycrystalline silicon may be deposited directly on a substrate, or may be formed by crystallizing amorphous silicon deposited through a plasma enhanced chemical vapor deposition (PECVD) method or by a low pressure chemical vapor deposition (LPCVD) method. Methods of crystallizing amorphous silicon may be classified into a solid phase crystallization (SPC) method, a metal induced crystallization (MIC) method, an excimer laser annealing (ELA) method, and a sequential lateral solidification (SLS) method. Among these various different methods of crystallizing amorphous silicon, the ELA method using ultraviolet (UV) light produced by an excimer laser is commonly used. In the ELA method, a layer of amorphous silicon is annealed for a short time period. Thus, deterioration of the substrate does not occur even under a melting temperature of silicon. Accordingly, a substrate of low cost, such as a glass substrate, may be used to fabricate an LCD device using polycrystalline silicon.
When a TFT is used as a switching element in a pixel region of an LCD device, a relatively low off-current is required for the TFT (i.e., a current flowing through a drain electrode when a turn-off voltage is applied to a gate electrode of a TFT). Since a p-Si TFT has a higher field effect mobility than an a-Si TFT, the p-Si TFT has a higher on-current (i.e., a current flowing through a drain electrode when a turn on voltage is applied to a gate electrode of a TFT) than the a-Si TFT. However, since a p-Si TFT has a higher leakage current at a junction between an intrinsic active region and a high doped drain region than an a-Si TFT, the p-Si TFT has a higher off-current than the a-Si TFT. Accordingly, the higher off-current is a disadvantage of using the p-Si TFT as a switching element in a pixel region of an LCD device. To reduce the off-current of a p-Si TFT, a lightly doped drain (LDD) region that is doped with impurities of lower concentration than a drain region is formed between an active region and a drain region.
FIG. 1 is a cross-sectional view illustrating a display area of an array substrate for an LCD device according to the related art. In FIG. 1, a semiconductor layer 13 of polycrystalline silicon is formed on a substrate 10 in a switching area “TrA” of each pixel region “P.” The semiconductor layer 13 includes an active region 13a, LDD regions 13b and 13c at both sides of the active region 13a, and source and drain regions 13d and 13e at outer sides of the LDD regions 13b and 13c. The active region 13a is not doped with impurities to remain as an intrinsic silicon layer. In addition, the LDD regions 13b and 13c are doped with low concentration impurities, and the source and drain regions 13d and 13e are doped with high concentration impurities.
A gate insulating layer 16 is formed on the semiconductor layer 13, and a gate electrode 21 is formed on the gate insulating layer 16. An interlayer insulating layer 25 having first and second semiconductor contact holes 28a and 28b is formed on the gate electrode 21. The first and second semiconductor contact holes 28a and 28b expose the source and drain regions 13d and 13e, respectively. The source and drain electrodes 30 and 32 are formed on the interlayer insulating layer 25. The source electrode 30 is connected to the source region 13d through the first semiconductor contact hole 28a, and the drain electrode 32 is connected to the drain region 13e through the second semiconductor contact hole 28b. 
A passivation layer 35 is formed on the source and drain electrodes 30 and 32. The passivation layer 35 has a drain contact hole 38 exposing the drain electrode 32. A pixel electrode 40 connected to the drain electrode 32 through the drain contact hole 38 is formed on the passivation layer 35.
The semiconductor layer 13 is classified into three regions: an intrinsic region (active region 13a), a low doped region (LDD regions 13b and 13c), and a high doped region (source and drain regions 13d and 13e). Even though a leakage current of the p-Si TFT is reduced due to the LDD regions 13b and 13c, an additional mask process is required to form the LDD regions 13b and 13c. Accordingly, fabrication cost is increased, and production yield is reduced.
In an LCD device using polycrystalline silicon, a driving circuit including a CMOS circuit is integrated in a substrate having a display area. FIG. 2 is a cross-sectional view illustrating a driving circuit area of an array substrate for an LCD device according to the related art. In FIG. 2, a CMOS inverter having an N-type TFT (nTr) and a P-type TFT (pTr) is formed in a driving circuit area (DCA). The N-type TFT (nTr) and the P-type TFT (pTr) include an N semiconductor layer 53 and a P semiconductor layer 54, respectively. The N-type semiconductor layer 53 in an N-type area (nA) includes an N-type active region 53a, N-type LDD regions 53b and 53c at both sides of the N-type active region 53a, and N-type source and drain regions 53d and 53e at outer sides of the N-type LDD regions 53b and 53c. In addition, the P-type semiconductor layer 54 in a P-type area “pA” includes a P-type active region 54a, and P-type source and drain regions 54b and 54c at both sides of the P-type active region 54a. Since three doping steps for high concentration N-type impurities (n+), high concentration P-type impurities (p+) and low concentration N-type impurities (n−) are required for a fabrication process of the CMOS inverter, the fabrication process of the related art CMOS inverter includes at least three mask steps. Increase in a mask step causes increase in fabrication cost and reduction in production yield.